Understanding The 100G Ethernet Client


The client interface for 100Gb/s Ethernet is standardised in IEEE802.3ba as an amendment to the full 802.3 specification.

The 100G Ethernet IEEE Model defines a new architecture the fits within the OSI Physical Layer

The client interface for Ethernet at 40Gb/s and 100Gb/s is fundamentally different from the earlier 10Gb/s and lower rates. At these lower rates the interface is specified as a serial stream of data that is line coded in a specific manner for transmission over copper or fibre. In terms of the fibre connectivity a single transmit and single receive fibre are used for bidirectional transmission. At the higher speed rates including 100G Ethernet the interface utilisises parallel streams of data that are transmitted either over multiple fibres or multiple WDM wavelengths within a single fibre.

In order to achieve this parallel transmission a new architecture was introduced below the MAC layer that is unique to the 40G and 100G Ethernet rates.

The Ethernet frame itself remains unchanged. The MAC remains the same as the MAC used at lower speed rates and includes the pre-amble, source and destination MAC address, Ethertype field, payload area, FCS and IFG.

Ethernet frames are line coded and distributed across 20 PCS Lanes
Ethernet frames are line coded and distributed across 20 PCS Lanes

The Ethernet frames are serialised into a stream of 64b/66b blocks in a similar manner to the line coding used for 10Gb/s Ethernet. The blocks also include a sync header for block framing.

The blocks are then distributed across a set of 20 Physical Coding Sublayer (PCS) Lanes. These lanes are a logical construct and are not presented in any physical medium to the network. Within each lane Alignment Markers are inserted. These markers are introduced outside of the line coded blocks and are not fed through the line coder mechanism, as such they have only a set of pre-defined values that are DC balanced and therefore can be placed directly on to the physical line. The alignment markers identify each of the 20 PCS lanes, allowing far-end identification of each lane.

The PCS Lane identification is a key factor in reconstruction of the 100G signal at the far end and testing the PCS Lanes is critical in a 100G Ethernet test scenario.

The PCS Lanes are bit-multiplexed into 10 lanes that form the 100G Attachment Unit Interface (CAUI). The CAUI is the electrical interface that is presented to the optical transponder, in general cases for optical transport applications the transponder used is a CFP transponder. There are several defined CFP transponder variants that will be discussed in later articles. In this example we will consider the LR4 CFP module.




The LR4 physical interface is defined as 4 WDM wavelengths around the 1305nm wavelength. Regardless of the CFP type the CAUI interface remains standard – a 10 x 10G electrical interface.

The PCS lanes are bit-muxed into 10 CAUI lanes which is the electrical interface to the CFP transponder
The PCS lanes are bit-muxed into 10 CAUI lanes which is the electrical interface to the CFP transponder

Within the LR4 interface is a module known as a gearbox. The gearbox takes the 10 lane input in and outputs 4 x 25G electrical lanes. Each of these lanes is then attached to a 25G laser and these 4 lasers are optically multiplexed onto a single fibre output.

In this manner the total Ethernet bandwidth is now transmitted across 4 x 25G optical wavelengths in parallel.

At the receive end the reverse mechanism is used to de-multiplex the four wavelengths out to the CAUI and then out to the PCS lanes. It is only at the PCS lane level that any reconstruction of the serial data is performed, as it is necessary to utilise the Alignment Markers to perform the recombination of the line coded blocks into the correct order. Due to this process it is not important which order the PCS Lane to CAUI Lane multiplex process is carried out, in fact as it is a simple bitmux operation with no indicator mechanism within the CAUI the two PCS Lanes that are bitmuxed into a CAUI Lane may be reversed when they are extracted into a PCS construct. However due to the Alignment Marker extraction at the PCS the final block ordering will still be possible.

As is evident from this model the CFP module can no longer be considered a somple optical transponder and is in fact a complete electrical / optical sub-system in its own right. This necessitates an additional layer of testing that will focus entirely on the connectivity between two CFP interfaces in adjacent network devices.